Public Title Parallel Algorithms for Sparse Matrix Simulations Division Lead Inventor Cauley, Stephen Public Description Performing simulations of very large scale integrated (VLSI) systems is a necessary step prior to building the system hardware. VLSI simulations involve calculating sparse matrices and differential equations. These math operations require large amounts of processing capabilities (computational power and memory). A greater demand is placed on the processing capability when the feature size of VLSI circuits is scaled downward. Such aggressive scaling requires simulation methods that take into account the interconnect effects (stray capacitance and inductive effects). Purdue University inventors have developed a novel method of simulating VLSI circuits, which takes into account the interconnect effects. This method achieves a significant reduction in the processing capability with little sacrifice in simulation accuracy. Patent Status Public References Key Words Mechanical Engineering/Computer Technology; Computer Technology Manager Hilton Turner Email haturner@prf.org Telephone 765-588-3479 Fax 765-463-3486   Back to List